In order to reduce the electric resistance of the gate electrode of a MOS transistor, for example, a technique has been developed for forming a silicide layer over the gate electrode by depositing a metal layer, such as of Ni, Ti or Co, on the gate electrode and then allowing the metal layer to react with the silicon of the gate electrode. Also, full silicidation has been studied for fully siliciding the gate electrode.
The full silicidation is also applied to a so-called self-aligned silicide (hereinafter referred to as salicide) technique for siliciding the upper portions of the source/drain regions as well as the gate electrode. In this instance, the upper portions of the source/drain regions are silicided while the gate electrode is entirely silicided.
For example, a salicide technique is described in K. G. Anil, et al., p. 190, 2004 Symposium on VLSI Technology Digest of Technical Papers.
FIGS. 1A to 1C and FIGS. 2A and 2B are sectional views of a process of a method for manufacturing a MOS transistor to which full silicidation is applied utilizing a salicide technique.
As illustrated in FIG. 1A, an element isolation region 211 is formed in a semiconductor substrate 201, and a gate electrode 203 of, for example, polycrystalline silicon is formed on the active region isolated by the element isolation region 211 with a gate insulating layer 202 therebetween. Source/drain regions 204 partially overlapping with extension regions 204a are formed in the surface of the semiconductor substrate 201 at both sides of the gate electrode 203. A cap layer 205 is formed of, for example, silicon nitride on the surface of the gate electrode 203, and a side wall insulating film 206 is formed of, for example, silicon oxide, on the side surface of the gate electrode 203. In this state, a Ni layer 207, which is a siliciding metal to be silicided, and a TiN layer 208 acting as a cap layer are formed in that order over the entire surface of the semiconductor substrate 201, and are then subjected to first annealing at 300° C. or less. A Ni2Si layer 209 is thus formed in the surfaces of the source/drain regions 204.
The unreacted Ni layer 207 and TiN layer 208 are selectively removed by wet etching, and then second annealing is performed at about 300° C. to 450° C., as illustrated in FIG. 1B. The Ni2Si layer 209 at the surface of the source/drain regions 204 is thus converted to a NiSi layer 210. Since the upper surface of the gate electrode 203 is covered with the cap layer 205, the gate electrode 203 is not silicided by the first and the second annealing for silicidation.
After the cap layer 205 is selectively removed by wet etching, an insulating layer, for example, an insulating interlayer 212 including silicon nitride, is deposited over the entire surface of the semiconductor substrate 201 to a thickness in which the gate electrode 203 may be buried, as illustrated in FIG. 1C. The insulating interlayer 212 and the side wall insulating film 206 are subjected to chemical-mechanical polishing (CMP) until the surface of the gate electrode 203 is exposed.
A Ni layer 213, which is to be silicided, is formed over the surface of the silicon nitride layer 212 including the surface of the gate electrode 20, as illustrated in FIG. 2A. Then, third annealing is performed at a temperature of about 300° C. to 500° C., such as 400° C., to silicide the entirety of the gate electrode 203, thus forming a fully silicided gate electrode 214, as illustrated in FIG. 2B. After selectively removing the unreacted Ni layer 213 by wet etching, contact holes, conductors and an insulating interlayer are formed. The present inventors have made patent applications related to silicidation, such as Japanese Laid-Open Patent Publication Nos. 2009-76605 and 2008-78559.
If full silicidation is performed in the salicide technique, the in-plane uniformity in flatness of the insulating interlayer 212, the gate electrode 203 and the side wall insulating film 206 is undesirably degraded by polishing the insulating interlayer 212 to planarize by CMP for the third annealing.
Polycrystalline silicon, which is the material of the gate electrode 203, and silicon oxide, which is the material of the side wall insulating film 206, have higher etching rates than silicon nitride, which is the material of the insulating interlayer 212. Accordingly, the level of the upper surface of the insulating interlayer 212 becomes lower than the levels of the upper surfaces of the gate electrode 203 and the side wall insulating film 206 at the time when CMP is completed. The in-plane uniformity in flatness of the insulating interlayer 212, the gate electrode 203 and the side wall insulating film 206 becomes insufficient.
A plurality of gate electrodes 203 are formed on a semiconductor substrate 201, and they may be disposed close to each other or apart from each other depending on the region. In this instance, CMP is performed on the silicon nitride layer covering the plurality of gate electrodes 203, and the above-mentioned difference in etching rate causes the degree of polishing the insulating interlayer 212 to differ depending on the density of the gate electrodes 203.
The plurality of gate electrodes 203 are present with various gate lengths. In this instance, the above-mentioned difference in etching rate causes the degree of polishing the insulating interlayer 212 to differ depending on the gate length of the gate electrode 203.
The difference in degree of polishing the insulating interlayer 212 varies the contact area between the siliciding metal and the gate electrodes 203, and consequently results in nonuniformity of the resulting silicide.